The present invention generally relates to integrated circuits, and, more particularly, to a low leakage flip-flop circuit.
Integrated circuits (ICs) or chips such as system-on-chips (SoCs) have many digital circuit modules for performing various functions on a single chip. Power consumption in integrated circuits is a major concern, especially in handheld devices such as mobile phones, smart phones, laptops, cameras, personal digital assistants (PDAs), and tablets. With advancements in technology, more and more functionality is being implemented in an integrated circuit by increasing the number of transistors in the chip. This increase in the number of circuits increases power consumption and in the heat generated by the chip, which can adversely affect the performance of devices that include such chips.
One known technique to reduce power consumption is to configure the chip to operate in multiple power modes, such as high and low power modes. In the low power mode, one or more circuit modules are turned off. Another known technique is to have multiple, different power domains. For example, one power domain will operate at 5 v and another domain will operate at say 1.8 v.
One of the basic components of a digital module is a flip-flop. Flip-flops can be positive or negative edge-triggered. A positive edge-triggered flip-flop changes its output at a positive edge of a clock signal and a negative edge-triggered flip-flop changes its output at a negative edge of the clock signal.
Each power domain includes a power management unit (PMU). The PMUs control the power consumption of the flip-flops located within the respective power domains by setting the flip-flops in an active mode when the SoC is in the high power mode and setting the flip-flops in a sleep mode when the SoC is in the low-power mode, thereby reducing overall power consumption. However, due to the presence of multiple power domains, a power ramp up latency is introduced in the chip when the flip-flops are toggled between the active and sleep modes. Power ramp up latency refers to the time required to switch a voltage level of a signal from one voltage level to another. Power ramp up latency can reduce the overall performance of the chip, negating the benefit of the multiple power domains.
FIG. 1A is a schematic block diagram of a conventional IC 100 that includes a clock-gating cell 102 and a flip-flop 104. The IC 100 is operable in high and low power modes and includes high and low power domains (collectively not shown).
The clock-gating cell 102 includes a first latch 106 and an AND gate 108. The first latch 106 has an input terminal for receiving an enable signal (VEN), a clock terminal for receiving a clock signal (VCLK), a first power terminal for receiving a supply voltage signal (VDD), a second power terminal connected to ground, and an output terminal for outputting a latched-enable signal (VLEN). The enable signal (VEN) is generated when the IC 100 toggles between the high and low power modes. For instance, when a user presses a sleep button of a smart phone to set the smart phone in a low power mode such as a sleep mode, a processor (not shown) of the IC 100 included in the smart phone generates the enable signal (VEN) to deactivate logic circuits of the low power domain of the IC 100.
The first latch 106 is activated when the clock signal (VCLK) is at a logic low state and deactivated when the clock signal (VCLK) is at a logic high state.
The AND gate 108 has a first input terminal for receiving the clock signal (VCLK), a second input terminal connected to the output terminal of the first latch 106 for receiving the latched-enable signal (VLEN) and an output terminal for generating the gated-clock signal (VGATED-CLK).
The flip-flop 104 includes second and third latches 110 and 112 and a NOT gate 114. The flip-flop 104 is a positive-edge triggered flip-flop. The second and third latches 110 and 112 operate in a master-slave configuration.
The second latch 110 operates as a master latch and has an input terminal for receiving an input signal (VIN), a clock terminal connected to the output terminal of the AND gate 108 for receiving the gated-clock signal (VGATED-CLK), a first power terminal for receiving the supply voltage signal (VDD), a second power terminal connected to ground, and an output terminal for outputting an intermediate output signal (VINT). The second latch 110 is activated when the gated-clock signal (VGATED-CLK) is at a logic low state and deactivated when the gated-clock signal (VGATED-CLK) is at a logic high state.
The third latch 112 operates as a slave latch and has an input terminal connected to the output terminal of the second latch 110 for receiving the intermediate output signal (VINT) r a clock terminal connected to the output terminal of the AND gate 108 by way of the NOT gate 114 for receiving an inverted gated-clock signal (VINV-GATED-CLK), a first power terminal for receiving the supply voltage signal (VDD), a second power terminal connected to ground, and an output terminal for outputting an output signal (VOUT). The third latch 112 is activated when the inverted gated-clock signal (VINV-GATED-CLK) is at a logic low state and deactivated when the inverted gated-clock signal is at a logic high state.
FIG. 1B is a timing diagram illustrating the operation of the conventional IC 100. From T0-T4, the enable signal (VEN) and the latched-enable signal (VLEN) are at logic high states. Thus, the clock-gating cell 102 outputs the clock signal (VCLK) as the gated-clock signal (VGATED-CLK) from T0-T4. At time T4, the enable signal (VEN) and the latched-enable signal (VLEN) toggle from high to low. Thus, the clock-gating cell 102 outputs the gated-clock signal (VGATED-CLK) at a logic low state based on the latched-enable signal (VLEN).
From T4-T5, the gated-clock signal (VGATED-CLK) is at a logic low state, and hence, the second latch 110 is activated and the intermediate output signal (VINT) is retained at the same state as the input signal (VIN), i.e., the intermediate signal (VINT) toggles to a logic high state. However, the third latch 112 receives the logic high inverted gated-clock signal (VINV-GATED-CLK) and hence, is deactivated. The logic state of the output signal (VOUT) remains same as the previous logic state, i.e., at a logic low state. Similarly, for T5-T8, the enable signal (VEN) is low and hence, the intermediate signal follows the input signal (VIN) and the output signal (VOUT) does not change from T5-T8.
At the end of time period T7-T8, the enable signal (VEN) toggles from low to high. Thus, after time T8, the latched-enable signal (VEN) toggles from low to high and the IC 100 operates the same as from time period T0-T4.
As described above, from T4-T8, the flip-flop 104 is deactivated, i.e., the third latch 112 is deactivated. However, the second latch 110 is active, thereby leading to unnecessary power consumption. The flip-flop 104 is deactivated when the gated-clock signal (VGATED-CLK) is at the logic low state, i.e., when the clock signal (VCLK) and enable signal (VEN) are at logic low states. Subsequently, the PMU generates and provides the enable signal (VEN) to the IC 100, thereby setting the IC 100 in the low-power mode.
SoCs include circuits that are functionally and structurally similar to the IC 100, and hence, each such circuit receives the enable signal (VEN), i.e., the PMU deactivates the circuits when the SoC is in the low-power mode. As the circuits are structurally and functionally similar to the IC 100, the conventional technique does not leverage the SoC architecture and hence, does not provide optimized power solutions based on the SoC architecture. Further, toggling the flip-flops from the low power mode to the active mode introduces latency due to charging of internal components of the flip-flops. Examples of such internal components include internal capacitive or inductive nodes.
Therefore, it would be advantageous to have an integrated circuit with a flip-flop circuit that consumes less power and does not increase design complexities.